Decoupled Access DRAM Architecture
نویسندگان
چکیده
This paper discusses an approach to reducing mem ory latency in future systems It focuses on systems where a single chip DRAM processor will not be fea sible even in years e g systems requiring a large memory and or many CPU s In such systems a solu tion needs to be found to DRAM latency and bandwidth as well as to inter chip communication Utilizing the projected advances in chip I O bandwidth we propose to implement a decoupled access execute processor where the access processor is placed in memory A program is compiled to run as a computational process and several access processes with the latter executing in the DRAM processors Instruction set extensions are discussed to support this paradigm Using multi level branch pre diction the access processor stays ahead of the execute processor and keeps the latter supplied with data The system reduces latency by moving address computation to memory and thus avoiding sending address to mem ory by the computational processor This and the fetch ahead capabilities of the access processor are combined with multiple DRAM streaming to improve perfor mance DRAM caching is assumed to be used to assist in this as well This work was supported in part by the University of Illi nois and National Science Foundation under Grant No US NSF
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